The pattern of bond pads on the active surface of an electronic component are typically redistributed to a pattern of terminals for electrical connection to other structures. This redistribution requires formation of several circuit patterns one on top of another. The circuit patterns are electrically isolated from one another by dielectric layers and are electrically interconnected by vias extending through the dielectric layers.
Each circuit pattern and associated dielectric layer requires several manufacturing operations and thus adds to the overall cost of the resulting electronic component package. Accordingly, it is desirable to minimize the number of circuit patterns while providing the desired redistribution.
In the following description, the same or similar elements are labeled with the same or similar reference numbers.